1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly, to a semiconductor integrated circuit device provided with at least two resistor layers of the same resistor value.
2. Description of the Prior Art
In semiconductor integrated circuits, where resistors and active devices are formed on one chip, there are occasions when a plurality of resistors are formed to be of the same value.
For example, in a circuit where a plurality of resistors R1 to R6 are connected to an operational amplifier 1 as shown in FIG. 4, the resistors R1, R3 and R6 are formed to be of the same value (i.e. R1=R3=R6). This circuit is used for an isolation circuit shown in FIG. 5. The isolation circuit is a circuit for canceling noise generated by an engine before the noise intrudes into a power amplifier in an car audio apparatus. In the isolation circuit, noise generated by a noise source 4 intrudes through a path 5 into a minus input terminal of the operational amplifier 1; it also intrudes through a path 6 where a signal source 3 and a buffer amplifier 2 are present into a plus input terminal of the operational amplifier 1. When this happens, as conventionally known, the noise which intrudes into the operational amplifier 1 through the paths 5 and 6 is canceled if the following conditions are satisfied:
(1) R1=R3=R6; and PA1 (2) a combined resistance value of the resistors R4 and R5=a combined resistance value of the resistors R2 and R3. If these conditions (1) and (2) are fulfilled, no noise reaches the power amplifier connected to the output side of the operational amplifier 1.
When such a circuit is provided in the form of an integrated circuit, conventionally, the resistors R6, R2 and R3 are formed as shown in FIG. 1. Numeral 10 is a semiconductor substrate. Numeral 11 is a land which is an n-type semiconductor layer formed by an epitaxial growth. Three p+resistor layers 12, 13 and 14 are provided in the land 11. The p.sup.+ resistor layers 12, 13 and 14 correspond to the resistors R6, R2 and R3 of FIG. 4, respectively.
To the land 11, a voltage Vcc is applied from a terminal 15 through an n.sup.+ area 16. To the resistor layer 12, a voltage is applied from a terminal 17. To the resistor layer 13, the voltage Vcc is applied from a terminal 18. The left end of the resistor layer 14 is connected to ground. The left ends of the resistor layers 12 and 13 are connected to the right end of the resistor layer 14 through a line 19. Numeral 20 is a depletion layer created by providing a reverse bias to a p-n junction. According to the above-mentioned condition (1), the resistor layer 12 (R6) and the resistor layer 14 (R3) must be of the same value in FIG. 1.
With this arrangement, however, since it is extremely difficult to form the resistor layers 12 and 14 (i.e. the resistors R6 and R3) to be of the same value, the above-mentioned conditions (1) and (2) for noise cancellation cannot be satisfied. This problem will be explained with reference to FIG. 2. In FIG. 2, A is a reference potential point (hereinafter referred to as reference point). Assuming that a collector-base junction can be approximated by a graded junction, a width dm of the depletion layer 20 with respect to a potential difference (Vcc-Va) between a potential Va at a point which is a distance a away from the reference point A and the voltage Vcc applied to the land 11 is expressed by the following equation (1): ##EQU1## where b is a grade of the junction, .epsilon.si is a specific inductive capacity, so is a dielectric constant in a vacuum, q is an electric charge, and K is a constant.
A spread dl of the depletion layer toward a base diffusion layer at the time of n-type isolation bias is generally shown by a monograph of the Gaussian distribution. Assuming now that dl=B.dm (where B&lt;1), the sheet resistance .rho.s is where .rho. is a volume resistivity and xi is a depth of the resistor layer at a distance x from a reference point A. If the bias voltage (Vcc-Va) is larger than this, the value of the sheet resistance .rho.s increases. FIG. 3 graphically shows a relationship between the bias voltage (Vcc-Va) and the sheet resistance .rho.s.
As described above, the junction bias voltage varies depending on the voltage applied to the resistor layer, so that the resistance value of the resistor layer varies. As a result, the resistance values of two resistor layers are not of the same value if they are formed under the same condition (i.e. size, etc.) It is difficult to equalize the values by changing the impurity concentration or by adjusting the size.